//------------------------------------------------
// aludec.v
//
// James Forrest, 2013
// Based on code by:
// David_Harris@hmc.edu 3 November 2005
//
// Pipelined MIPS processor
//------------------------------------------------

module aludec(input      [5:0] funct,
              input      [3:0] aluop,
              output reg [3:0] alucontrol);

    always @(*)
        case(aluop)
        4'b1000: alucontrol <= 4'b0010;  // add
        4'b1001: alucontrol <= 4'b0110;  // sub
        4'b1010: alucontrol <= 4'b0111;  // slt
        4'b1110: alucontrol <= 4'b1011;  // sltu
        4'b1011: alucontrol <= 4'b1111;  // lui
        4'b0001: alucontrol <= 4'b0000;  // and
        4'b0010: alucontrol <= 4'b0001;  // or
        4'b0011: alucontrol <= 4'b0100;  // xor
        4'b0000: casex(funct)            // RTYPE
            6'b000000: alucontrol <= 4'b1000; // sll
            6'b000010: alucontrol <= 4'b1001; // srl
            6'b000011: alucontrol <= 4'b1010; // sra
            6'b000100: alucontrol <= 4'b1100; // sllv
            6'b000110: alucontrol <= 4'b1101; // srlv
            6'b000111: alucontrol <= 4'b1110; // srav
            6'b10000?: alucontrol <= 4'b0010; // ADD/addu
            6'b10001?: alucontrol <= 4'b0110; // SUB/subu
            6'b100100: alucontrol <= 4'b0000; // AND
            6'b100101: alucontrol <= 4'b0001; // OR
            6'b100110: alucontrol <= 4'b0100; // xor
            6'b100111: alucontrol <= 4'b0101; // nor
            6'b101010: alucontrol <= 4'b0111; // SLT
            6'b101011: alucontrol <= 4'b1011; // sltu
            default:   alucontrol <= 4'bxxxx; // ???
        endcase
        default: alucontrol <= 4'bxxxx; // ???
    endcase
endmodule
